SMAT focusses on developing intelligent sensing technologies to support and enforce traffic management of the SRT layer. This involves the development of robust and secure vision based sensing methods for collaborative computing and crowd sourcing. The underlying research in SMAT will lead to a better understanding of the advantage and limitations of utilizing real-time data to assist travellers in an Agile Transportation System.
Research
Architecture-Aware Algorithms for Low-Cost Sensing
In order to provide for scalable vision based crowd sourcing for a dense urban public transport system, such as in Singapore, low-complexity sensing techniques are critical to justify mass volume adoption. Architecture-efficient algorithms are being developed to implement low-complexity and real-time vision-based traffic sensors. The robustness of such algorithms will be evaluated to ensure they withstand the varying weather conditions and complex conditions on a road segment.
Techniques for Vehicle Breakdown and Accident Detection
Vision based techniques are being devised to accurately establish traffic incidents and traffic violations. Computationally inexpensive computer vision algorithms are being developed to perform localized monitoring of current traffic condition. Vision based sensors will be used to detect traffic law violations (e.g. entering priority lanes, illegal parking in priority lanes, illegal turns, etc.). It is envisaged that mass-deployable real-time law enforcement solutions would ultimately ensure smooth traffic flow for SRTs.
Real-Time Scene Understanding for Congestion Management
Persistent congestions can be automatically identified through real-time scene understanding techniques. Crowd sourcing methods are being adopted by installing scene understanding sensors in vehicles to detect congestion. The relevant authorities can then take necessary actions to alleviate such unanticipated persistent congestion patterns that emerge over time.
Passive Sensing Techniques using Smartphone Location Data
The problem of inferring the mobility details of users from sequences of smartphone location samples involves considerable uncertainty, especially if the data is noisy and temporally sparse. Therefore, we intend to adopt a suitable probabilistic framework for solving this problem. To be able to process real-time data from a large number of users, the algorithms should have low latency and high computational efficiency. Therefore, are exploring optimization techniques to reduce the runtime and latency of the proposed methods. The developed solutions will be subjected to extensive evaluations using both real data as well as synthetic data obtained from traffic simulation environments. Robust statistical methods will be explored for aggregating information extracted from individual mobility traces in order to estimate the overall travel demand.
Secure Autonomous Traffic Security
A security-enabled sensory network protocol that satisfies real-time constraints is being developed using a virtual traffic simulation environment. The proposed network protocol will be deployed and benchmarked with off-the-shelf micro-controllers and FPGA development boards. Side-channel attack/tamper-resistant low-cost cryptographic accelerators for Internet of Things (IoT) communication will be developed such that the encryption/decryption modules are physically resistant to reasonably sophisticated side-channel attacks.
Publications
[67]
D. Piyasena, R. Wickramasinghe, D. Paul, S. K. Lam, and M. Wu,“Lowering dynamic power of a stream-based cnn hardware accelerator,”in 2019 IEEE 21st International Workshop on Multimedia Signal Processing (MMSP),Kuala Lumpur, Malaysia,Sep.2019,pp. 1–6,DOI: 10.1109/MMSP.2019.8901777.
@inproceedings{piyasena2019loweringSMAT,
title
=
{Lowering Dynamic Power of a Stream-based CNN Hardware Accelerator},
author
=
{Piyasena, Duvindu and Wickramasinghe, Rukshan and Paul, Debdeep and Lam, Siew Kei and Wu, Meiqing},
booktitle
=
{2019 IEEE 21st International Workshop on Multimedia Signal Processing (MMSP)},
year
=
{2019},
month
=
Sep,
pages
=
{1--6},
location
=
{Kuala Lumpur, Malaysia},
doi
=
{10.1109/MMSP.2019.8901777},
}
[66]
D. Piyasena, R. Wickramasinghe, D. Paul, S. K. Lam, and M. Wu,“Reducing dynamic power in streaming cnn hardware accelerators by exploiting computational redundancies,”in 2019 29th International Conference on Field Programmable Logic and Applications (FPL),Barcelona, Spain, Spain,Sep.2019,pp. 354–359,DOI: 10.1109/FPL.2019.00063.
@inproceedings{piyasena2019reducingSMAT,
title
=
{Reducing Dynamic Power in Streaming CNN Hardware Accelerators by Exploiting Computational Redundancies},
author
=
{Piyasena, Duvindu and Wickramasinghe, Rukshan and Paul, Debdeep and Lam, Siew Kei and Wu, Meiqing},
booktitle
=
{2019 29th International Conference on Field Programmable Logic and Applications (FPL)},
year
=
{2019},
month
=
Sep,
pages
=
{354--359},
location
=
{Barcelona, Spain, Spain},
doi
=
{10.1109/FPL.2019.00063},
}
[65]
T. H. Pham, P. Tran, and S. K. Lam,“High-Throughput and area-optimized architecture for rbrief feature extraction,”IEEE Transactions on Very Large Scale Integration (VLSI) Systems,IEEE,pp. 747–756,Dec.2018,DOI: 10.1109/TVLSI.2018.2881105.
@article{pham2018highSMAT,
title
=
{High-Throughput and Area-Optimized Architecture for rBRIEF Feature Extraction},
author
=
{Pham, Thinh Hung and Tran, Phong and Lam, Siew Kei},
journal
=
{IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
year
=
{2018},
month
=
Dec,
pages
=
{747--756},
publisher
=
{IEEE},
doi
=
{10.1109/TVLSI.2018.2881105},
}
[64]
A. Baksi, D. Saha, and S. Sarkar,“To infect or not to infect: a critical analysis of infective countermeasures in fault attacks,”Journal of Cryptographic Engineering (JCEN),Springer,2020,accepted.
@article{baksi2020toSMAT,
title
=
{To Infect Or Not To Infect: A Critical Analysis Of Infective Countermeasures In Fault Attacks},
author
=
{Baksi, Anubhab and Saha, Dhiman and Sarkar, Sumanta},
journal
=
{Journal of Cryptographic Engineering (JCEN)},
year
=
{2020},
publisher
=
{Springer},
}
[63]
P. He, G. Jiang, S. K. Lam, and Y. Sun,“Learning heterogeneous traffic patterns for travel time prediction of bus journeys,”Information Sciences,vol. 512,Elsevier,pp. 1394–1406,Feb.2020,DOI: 10.1016/j.ins.2019.10.073.
@article{he2020learningSMAT,
title
=
{Learning heterogeneous traffic patterns for travel time prediction of bus journeys},
author
=
{He, Peilan and Jiang, Guiyuan and Lam, Siew Kei and Sun, Yidan},
journal
=
{Information Sciences},
volume
=
{512},
year
=
{2020},
month
=
feb,
pages
=
{1394--1406},
publisher
=
{Elsevier},
doi
=
{10.1016/j.ins.2019.10.073},
}
[62]
T. Perera, A. Prakash, D. Wijesundera, T. Srikanthan, and C. N. Gamage,“Cluster-first, route-second heuristic for EV scheduling in on-demand public transit,”in Proceedings of the 9th International Conference on Cybernetics and Intelligent Systems and Robotics, Automation and Mechatronics (CIS-RAM),2019,accepted.
@inproceedings{Perera2019bClusterSMAT,
title
=
{Cluster-first, Route-second Heuristic for {EV} Scheduling in On-demand Public Transit},
author
=
{Perera, Thilina and Prakash, Alok and Wijesundera, Deshya and Srikanthan, Thambipillai and Gamage, Chathura Nagoda},
booktitle
=
{Proceedings of the 9th International Conference on Cybernetics and Intelligent Systems and Robotics, Automation and Mechatronics (CIS-RAM)},
year
=
{2019},
}
[61]
T. Perera, A. Prakash, and T. Srikanthan,“Genetic algorithm based dynamic scheduling of EV in a demand responsive bus service for first mile transit,”in Proceedings of the 22nd International Conference on Intelligent Transportation Systems (ITSC),Auckland, New Zealand, New Zealand:IEEE,Oct.2019,pp. 3322–3327,DOI: 10.1109/ITSC.2019.8917141.
@inproceedings{Perera2019aGeneticSMAT,
title
=
{Genetic Algorithm Based Dynamic Scheduling of {EV} in a Demand Responsive Bus Service for First Mile Transit},
author
=
{Perera, Thilina and Prakash, Alok and Srikanthan, Thambipillai},
booktitle
=
{Proceedings of the 22nd International Conference on Intelligent Transportation Systems (ITSC)},
year
=
{2019},
month
=
oct,
location
=
{Auckland, New Zealand, New Zealand},
pages
=
{3322--3327},
publisher
=
{IEEE},
doi
=
{10.1109/ITSC.2019.8917141},
}
[60]
P. He, Y. Sun, G. Jiang, and S. K. Lam,“Predicting travel time of bus journeys with alternative bus services,”in Proceedings of the 2019 IEEE International Conference on Data Mining Workshops, ICDM Workshops 2019,Beijing, China:IEEE,Nov.2019,pp. 114–123,DOI: 10.1109/ICDMW.2019.00027.
@inproceedings{He2019PredictingSMAT,
title
=
{Predicting Travel Time of Bus Journeys with Alternative Bus Services},
author
=
{He, Peilan and Sun, Yidan and Jiang, Guiyuan and Lam, Siew Kei},
booktitle
=
{Proceedings of the 2019 IEEE International Conference on Data Mining Workshops, ICDM Workshops 2019},
year
=
{2019},
month
=
nov,
location
=
{Beijing, China},
pages
=
{114--123},
publisher
=
{IEEE},
doi
=
{10.1109/ICDMW.2019.00027},
}
[59]
G. Jiang, S. K. Lam, F. Ning, P. He, and J. Xie,“Peak-hour vehicle routing for first-mile transportation: problem formulation and algorithms,”IEEE Transactions on Intelligent Transportation Systems,IEEE,pp. 1–14,2019,DOI: 10.1109/TITS.2019.2926065.
@article{Jiang2019PeakSMAT,
title
=
{Peak-hour Vehicle Routing for First-mile Transportation: Problem Formulation and Algorithms},
author
=
{Jiang, Guiyuan and Lam, Siew Kei and Ning, Fangxin and He, Peilan and Xie, Jidong},
journal
=
{IEEE Transactions on Intelligent Transportation Systems},
year
=
{2019},
pages
=
{1--14},
publisher
=
{IEEE},
doi
=
{10.1109/TITS.2019.2926065},
}
[58]
G. R. Jagadeesh and T. Srikanthan,“Fast computation of clustered many-to-many shortest paths and its application to map matching,”ACM Transactions on Spatial Algorithms and Systems,vol. 5,no. 3,ACM,pp. 17:1–17:20,Aug.2019,DOI: 10.1145/3329676.
@article{Jagadeesh2019fastSMAT,
title
=
{Fast Computation of Clustered Many-to-many Shortest Paths and Its Application to Map Matching},
author
=
{Jagadeesh, George Rosario and Srikanthan, Thambipillai},
journal
=
{ACM Transactions on Spatial Algorithms and Systems},
volume
=
{5},
number
=
{3},
year
=
{2019},
month
=
aug,
pages
=
{17:1--17:20},
publisher
=
{ACM},
doi
=
{10.1145/3329676},
}
[57]
T. Perera, A. Prakash, and T. Srikanthan,“Genetic algorithm based EV scheduling for on-demand public transit system,”in Proceedings of the 2019 International Conference on Computational Science – ICCS 2019,Faro, Portugal,Jun.2019,pp. 595–603,DOI: 10.1007/978-3-030-22750-0_56.
@inproceedings{Perera2019GeneticSMAT,
title
=
{Genetic Algorithm based {EV} Scheduling for On-demand Public Transit System},
author
=
{Perera, Thilina and Prakash, Alok and Srikanthan, Thambipillai},
booktitle
=
{Proceedings of the 2019 International Conference on Computational Science -- ICCS 2019},
year
=
{2019},
month
=
jun,
pages
=
{595--603},
location
=
{Faro, Portugal},
doi
=
{10.1007/978-3-030-22750-0_56},
}
[56]
K. Garg, N. Ramakrishnan, A. Prakash, and T. Srikanthan,“Rapid and robust background modeling technique for low-cost road traffic surveillance systems,”IEEE Transactions on Intelligent Transportation Systems,IEEE,pp. 1–12,May2019,DOI: 10.1109/TITS.2019.2917560.
@article{garg2019bRapidSMAT,
title
=
{Rapid and Robust Background Modeling Technique for Low-cost Road Traffic Surveillance Systems},
author
=
{Garg, Kratika and Ramakrishnan, Nirmala and Prakash, Alok and Srikanthan, Thambipillai},
journal
=
{IEEE Transactions on Intelligent Transportation Systems},
year
=
{2019},
month
=
may,
pages
=
{1--12},
publisher
=
{IEEE},
doi
=
{10.1109/TITS.2019.2917560},
}
[55]
Y. Sun, G. Jiang, S. K. Lam, S. Chen, and P. He,“Bus travel speed prediction using attention network of heterogeneous correlation features,”in Proceedings of the 2019 SIAM International Conference on Data Mining (SDM),Calgary, Alberta, Canada,May2019,pp. 73–81,DOI: 10.1137/1.9781611975673.9.
@inproceedings{Sun2019BusSMAT,
title
=
{Bus Travel Speed Prediction Using Attention Network of Heterogeneous Correlation Features},
author
=
{Sun, Yidan and Jiang, Guiyuan and Lam, Siew Kei and Chen, Shicheng and He, Peilan},
booktitle
=
{Proceedings of the 2019 SIAM International Conference on Data Mining (SDM)},
pages
=
{73--81},
year
=
{2019},
month
=
may,
location
=
{Calgary, Alberta, Canada},
organization
=
{SIAM},
doi
=
{10.1137/1.9781611975673.9},
}
[54]
K. Garg, N. Ramakrishnan, A. Prakash, S. Thambipillai, and P. Bhatt,“Rapid technique to eliminate moving shadows for accurate vehicle detection,”in Proceedings of the 2019 IEEE Winter Conference on Applications of Computer Vision (WACV),Hawaii, USA:IEEE,Jan.2019,pp. 1970–1978,DOI: 10.1109/WACV.2019.00214.
@inproceedings{garg2019aRapidSMAT,
title
=
{Rapid Technique to Eliminate Moving Shadows for Accurate Vehicle Detection},
author
=
{Garg, Kratika and Ramakrishnan, Nirmala and Prakash, Alok and Thambipillai, Srikanthan and Bhatt, Punit},
booktitle
=
{Proceedings of the 2019 IEEE Winter Conference on Applications of Computer Vision (WACV)},
year
=
{2019},
month
=
jan,
pages
=
{1970--1978},
location
=
{Hawaii, USA},
publisher
=
{IEEE},
doi
=
{10.1109/WACV.2019.00214},
}
[53]
A. Khalid, G. Paul, and A. Chattopadhyay,“Domain specific high-level synthesis for cryptographic workloads,”in Computer Architecture and Design Methodologies,Springer Singapore,2019,DOI: 10.1007/978-981-10-1070-5.
@inproceedings{Ayesha2019DomainSMAT,
title
=
{Domain Specific High-Level Synthesis for Cryptographic Workloads},
author
=
{Khalid, Ayesha and Paul, Goutam and Chattopadhyay, Anupam},
booktitle
=
{Computer Architecture and Design Methodologies},
year
=
{2019},
publisher
=
{Springer Singapore},
doi
=
{10.1007/978-981-10-1070-5}
}
[52]
D. Wijesundera, A. Prakash, T. Perera, K. Herath, and T. Srikanthan,“Wibheda+: framework for data dependency-aware multi-constrained hardware-software partitioning in FPGA-based SoCs for IoT applications,”in Proceedings of the 9th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies,Toronto, ON, Canada:ACM,Jun.2018,pp. 3:1–3:6,DOI: 10.1145/3241793.3241796.
@inproceedings{Wijesundera2018bFrameworkSMAT,
title
=
{Wibheda+: Framework for Data Dependency-aware Multi-constrained Hardware-software Partitioning in {FPGA}-based {SoCs} for {IoT} Applications},
author
=
{Wijesundera, Deshya and Prakash, Alok and Perera, Thilina and Herath, Kalindu and Srikanthan, Thambipillai},
booktitle
=
{Proceedings of the 9th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies},
year
=
{2018},
month
=
jun,
pages
=
{3:1--3:6},
location
=
{Toronto, ON, Canada},
publisher
=
{ACM},
doi
=
{10.1145/3241793.3241796},
}
[51]
D. Wijesundera, A. Prakash, T. Perera, K. Herath, and T. Srikanthan,“Wibheda: framework for data dependency-aware multi-constrained hardware-software partitioning in FPGA-based SoCs for IoT devices,”in Proceedings of the 26th IEEE International Symposium on Field-Programmable Custom Computing Machines,Boulder, CO, USA:IEEE,Apr.2018,pp. 213-213,DOI: 10.1109/FCCM.2018.00047.
@inproceedings{Wijesundera2018aFrameworkSMAT,
title
=
{Wibheda: Framework for Data Dependency-aware Multi-constrained Hardware-software Partitioning in {FPGA}-based {SoCs} for {IoT} Devices},
author
=
{Wijesundera, Deshya and Prakash, Alok and Perera, Thilina and Herath, Kalindu and Srikanthan, Thambipillai},
booktitle
=
{Proceedings of the 26th IEEE International Symposium on Field-Programmable Custom Computing Machines},
year
=
{2018},
month
=
apr,
pages
=
{213-213},
location
=
{Boulder, CO, USA},
publisher
=
{IEEE},
doi
=
{10.1109/FCCM.2018.00047},
}
[50]
M. Swagata, B. Debjyoti, T. Yaswanth, and A. Chattopadhyay,“ReRAM-based in-memory computation of galois field arithmetic,”in Proceedings of the IEEE/IFIP VLSI-SoC,Verona, Italy, Italy:IEEE,Oct.2018,pp. 1-6,DOI: 10.1109/VLSI-SoC.2018.8644772.
@inproceedings{Swagata2018ReRAMSMAT,
title
=
{{ReRAM}-based In-memory Computation of Galois Field Arithmetic},
author
=
{Swagata, Mandal and Debjyoti, Bhattacharjee and Yaswanth, Tavva and Chattopadhyay, Anupam},
booktitle
=
{Proceedings of the IEEE/IFIP VLSI-SoC},
year
=
{2018},
month
=
oct,
pages
=
{1-6},
location
=
{Verona, Italy, Italy},
publisher
=
{IEEE},
doi
=
{10.1109/VLSI-SoC.2018.8644772}
}
[49]
S. Kumar, S. Jha, S. K. Pandey, and A. Chattopadhyay,“A security model for intelligent vehicles and smart traffic infrastructure,”in Proceedings of the IEEE Intelligent Vehicles Symposium,Changshu, China:IEEE,Jun.2018,pp. 162-167,DOI: 10.1109/IVS.2018.8500423.
@inproceedings{Sachin2018ASMAT,
title
=
{A Security Model for Intelligent Vehicles and Smart Traffic Infrastructure},
author
=
{Kumar, Sachin and Jha, Sonu and Pandey, Sumit Kumar and Chattopadhyay, Anupam},
booktitle
=
{Proceedings of the IEEE Intelligent Vehicles Symposium},
year
=
{2018},
month
=
jun,
pages
=
{162-167},
location
=
{Changshu, China},
publisher
=
{IEEE},
doi
=
{10.1109/IVS.2018.8500423}
}
[48]
P. He, G. Jiang, S. K. Lam, and D. Tang,“Travel-time prediction of bus journey with multiple bus trips,”IEEE Transactions on Intelligent Transportation Systems,IEEE,2018,DOI: 10.1109/TITS.2018.2883342.
@article{He2018TravelSMAT,
title
=
{Travel-time Prediction of Bus Journey With Multiple Bus Trips},
author
=
{He, Peilan and Jiang, Guiyuan and Lam, Siew Kei and Tang, Dehua},
journal
=
{IEEE Transactions on Intelligent Transportation Systems},
year
=
{2018},
publisher
=
{IEEE},
doi
=
{10.1109/TITS.2018.2883342},
}
[47]
P. Tran, T. H. Pham, S. K. Lam, M. Wu, and B. A. Jasani,“Stream-Based ORB feature extractor with dynamic power optimization,”in Proceedings of the 2018 International Conference on Field-Programmable Technology (FPT),IEEE,Dec.2018,pp. 94–101,DOI: 10.1109/FPT.2018.00024.
@inproceedings{Tran2018StreamSMAT,
title
=
{Stream-Based {ORB} Feature Extractor with Dynamic Power Optimization},
author
=
{Tran, Phong and Pham, Thinh Hung and Lam, Siew Kei and Wu, Meiqing and Jasani, Bhavan A},
booktitle
=
{Proceedings of the 2018 International Conference on Field-Programmable Technology (FPT)},
pages
=
{94--101},
year
=
{2018},
month
=
dec,
publisher
=
{IEEE},
doi
=
{10.1109/FPT.2018.00024},
}
[46]
T. Perera, A. Prakash, and T. Srikanthan,“A hybrid methodology for optimal fleet management in an electric vehicle based flexible bus service,”in Proceedings of the 15th International Conference on Control, Automation, Robotics and Vision (ICARCV),Singapore,Nov.2018,pp. 331–336,DOI: 10.1109/ICARCV.2018.8581345.
@inproceedings{Perera2018bASMAT,
title
=
{A Hybrid Methodology for Optimal Fleet Management in an Electric Vehicle Based Flexible Bus Service},
author
=
{Perera, Thilina and Prakash, Alok and Srikanthan, Thambipillai},
booktitle
=
{Proceedings of the 15th International Conference on Control, Automation, Robotics and Vision (ICARCV)},
year
=
{2018},
month
=
nov,
pages
=
{331--336},
location
=
{Singapore},
doi
=
{10.1109/ICARCV.2018.8581345},
}
[45]
T. Perera, C. N. Gamage, A. Prakash, and T. Srikanthan,“A simulation framework for a real-time demand responsive public transit system,”in Proceedings of the 21st International Conference on Intelligent Transportation Systems (ITSC),Maui, Hawaii,Nov.2018,pp. 608–613,DOI: 10.1109/ITSC.2018.8569281.
@inproceedings{Perera2018aASMAT,
title
=
{A Simulation Framework for a Real-time Demand Responsive Public Transit System},
author
=
{Perera, Thilina and Gamage, Chathura Nagoda and Prakash, Alok and Srikanthan, Thambipillai},
booktitle
=
{Proceedings of the 21st International Conference on Intelligent Transportation Systems (ITSC)},
year
=
{2018},
month
=
nov,
pages
=
{608--613},
location
=
{Maui, Hawaii},
doi
=
{10.1109/ITSC.2018.8569281},
}
[44]
B. Jasani, S. K. Lam, P. K. Meher, and M. Wu,“Threshold-guided design and optimization for harris corner detector architecture,”IEEE Transactions on Circuits and Systems for Video Technology,pp. 1–1,Sep.2018,DOI: 10.1109/TCSVT.2017.2757998.
@article{Jasani2018ThresholdSMAT,
title
=
{Threshold-guided Design and Optimization for Harris Corner Detector Architecture},
author
=
{Jasani, Bhavan and Lam, Siew Kei and Meher, Pramod Kumar and Wu, Meiqing},
journal
=
{IEEE Transactions on Circuits and Systems for Video Technology},
year
=
{2018},
month
=
sep,
pages
=
{1--1},
doi
=
{10.1109/TCSVT.2017.2757998},
}
[43]
S. K. Lam, T. C. Lim, M. Wu, B. Cao, and B. Jasani,“Area-time efficient FAST corner detector using data-path transposition,”IEEE Transactions on Circuits and Systems II: Express Briefs,vol. 65,pp. 1224–1228,Sep.2018,DOI: 10.1109/TCSII.2017.2752259.
@article{Lam2018bAreaSMAT,
title
=
{Area-time Efficient {FAST} Corner Detector Using Data-path Transposition},
author
=
{Lam, Siew Kei and Lim, Teck Chuan and Wu, Meiqing and Cao, Bin and Jasani, Bhavan},
journal
=
{IEEE Transactions on Circuits and Systems II: Express Briefs},
volume
=
{65},
year
=
{2018},
month
=
sep,
pages
=
{1224--1228},
doi
=
{10.1109/TCSII.2017.2752259},
}
[42]
A. Prakash, C. T. Clarke, S. K. Lam, and T. Srikanthan,“Rapid memory-aware selection of hardware accelerators in programmable SoC design,”IEEE Transactions on Very Large Scale Integration Systems,vol. 26,pp. 445–456,Sep.2018,DOI: 10.1109/TVLSI.2017.2769125.
@article{prakash2018rapidSMAT,
title
=
{Rapid Memory-aware Selection of Hardware Accelerators in Programmable {SoC} Design},
author
=
{Prakash, Alok and Clarke, Christopher T. and Lam, Siew Kei and Srikanthan, Thambipillai},
journal
=
{IEEE Transactions on Very Large Scale Integration Systems},
volume
=
{26},
year
=
{2018},
month
=
sep,
pages
=
{445--456},
doi
=
{10.1109/TVLSI.2017.2769125},
}
[41]
D. Wijesundera, A. Prakash, T. Srikanthan, and A. Ihalage,“Framework for rapid performance estimation of embedded soft core processors,”ACM Transactions on Reconfigurable Technology and Systems,vol. 11,pp. 9:1–9:21,Jul.2018,DOI: 10.1145/3195801.
@article{Wijesundera2018FrameworkSMAT,
title
=
{Framework for Rapid Performance Estimation of Embedded Soft Core Processors},
author
=
{Wijesundera, Deshya and Prakash, Alok and Srikanthan, Thambipillai and Ihalage, Achintha},
journal
=
{ACM Transactions on Reconfigurable Technology and Systems},
volume
=
{11},
year
=
{2018},
month
=
jul,
pages
=
{9:1--9:21},
doi
=
{10.1145/3195801},
}
[40]
A. Baksi, V. Pudi, S. Mandal, and A. Chattopadhyay,“Lightweight ASIC implementation of AEGIS-128,”in Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI),Hong Kong, China,Jul.2018,pp. 251–256,DOI: 10.1109/ISVLSI.2018.00054.
@inproceedings{baksi2018LightweightSMAT,
title
=
{Lightweight {ASIC} Implementation of {AEGIS}-128},
author
=
{Baksi, Anubhab and Pudi, Vikramkumar and Mandal, Swagata and Chattopadhyay, Anupam},
booktitle
=
{Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)},
year
=
{2018},
month
=
jul,
pages
=
{251--256},
location
=
{Hong Kong, China},
doi
=
{10.1109/ISVLSI.2018.00054},
}
[39]
D. Bhattacharjee and A. Chattopadhyay,“Synthesis, technology mapping and optimization for emerging technologies,”in Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI),Hong Kong, China,Jul.2018,pp. 369–374,DOI: 10.1109/ISVLSI.2018.00074.
@inproceedings{Bhattacharjee2018SynthesisSMAT,
title
=
{Synthesis, Technology Mapping and Optimization for Emerging Technologies},
author
=
{Bhattacharjee, Debjyoti and Chattopadhyay, Anupam},
booktitle
=
{Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)},
year
=
{2018},
month
=
jul,
pages
=
{369--374},
location
=
{Hong Kong, China},
doi
=
{10.1109/ISVLSI.2018.00074},
}
[38]
M. A. Elmohr, S. Kumar, M. Khairallah, and A. Chattopadhyay,“A hardware-efficient implementation of CLOC for on-chip authenticated encryption,”in Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI),Hong Kong, China,Jul.2018,pp. 311–315,DOI: 10.1109/ISVLSI.2018.00064.
@inproceedings{Mahmoud2018ASMAT,
title
=
{A Hardware-efficient Implementation of {CLOC} for on-chip Authenticated Encryption},
author
=
{Elmohr, Mahmoud A. and Kumar, Sachin and Khairallah, Mustafa and Chattopadhyay, Anupam},
booktitle
=
{Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)},
year
=
{2018},
month
=
jul,
pages
=
{311--315},
location
=
{Hong Kong, China},
doi
=
{10.1109/ISVLSI.2018.00064},
}
[37]
R. Prasanna, S. Bhasin, J. Breier, and A. Chattopadhyay,“PPAP and iPPAP: PLL-based protection against physical attacks,”in Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI),Hong Kong, China,Jul.2018,pp. 620–625,DOI: 10.1109/ISVLSI.2018.00118.
@inproceedings{Ravi2018PPAPSMAT,
title
=
{{PPAP} and {iPPAP}: {PLL}-based Protection Against Physical Attacks},
author
=
{Prasanna, Ravi and Bhasin, Shivam and Breier, Jakub and Chattopadhyay, Anupam},
booktitle
=
{Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)},
year
=
{2018},
month
=
jul,
pages
=
{620--625},
location
=
{Hong Kong, China},
doi
=
{10.1109/ISVLSI.2018.00118},
}
[36]
K. Herath, A. Prakash, U. C. H. Kanewala, and T. Srikanthan,“Communication-aware module placement for power reduction in large FPGA designs,”in Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI),Hong Kong, China,Jul.2018,pp. 209–214,DOI: 10.1109/ISVLSI.2018.00047.
@inproceedings{Herath2018CommunicationSMAT,
title
=
{Communication-aware Module Placement for Power Reduction in Large {FPGA} Designs},
author
=
{Herath, Kalindu and Prakash, Alok and Kanewala, Udaree Chathurangee Hiranthika and Srikanthan, Thambipillai},
booktitle
=
{Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)},
year
=
{2018},
month
=
jul,
pages
=
{209--214},
location
=
{Hong Kong, China},
doi
=
{10.1109/ISVLSI.2018.00047},
}
[35]
T. Perera, A. Prakash, C. N. Gamage, and T. Srikanthan,“Hybrid genetic algorithm for an on-demand first mile transit system using electric vehicles,”in Proceedings of the 2018 International Conference on Computational Science – ICCS 2018,Wuxi, China,Jun.2018,pp. 98–113,DOI: 10.1007/978-3-319-93698-7_8.
@inproceedings{Perera2018HybridSMAT,
title
=
{Hybrid Genetic Algorithm for an On-demand First Mile Transit System Using Electric Vehicles},
author
=
{Perera, Thilina and Prakash, Alok and Gamage, Chathura Nagoda and Srikanthan, Thambipillai},
booktitle
=
{Proceedings of the 2018 International Conference on Computational Science -- ICCS 2018},
year
=
{2018},
month
=
jun,
pages
=
{98--113},
location
=
{Wuxi, China},
doi
=
{10.1007/978-3-319-93698-7_8},
}
[34]
K. Herath, A. Prakash, and T. Srikanthan,“Performance estimation of FPGA modules for modular design methodology using artificial neural network,”in Proceedings of the 14th International Symposium on Applied Reconfigurable Computing,Santorini, Greece,May2018,pp. 105–118,DOI: 10.1007/978-3-319-78890-6_9.
@inproceedings{Herath2018PerformanceSMAT,
title
=
{Performance Estimation of {FPGA} Modules for Modular Design Methodology using Artificial Neural Network},
author
=
{Herath, Kalindu and Prakash, Alok and Srikanthan, Thambipillai},
booktitle
=
{Proceedings of the 14th International Symposium on Applied Reconfigurable Computing},
year
=
{2018},
month
=
may,
pages
=
{105--118},
location
=
{Santorini, Greece},
doi
=
{10.1007/978-3-319-78890-6_9},
}
[33]
M. M. Wong, J. Haj-Yahya, S. Suman, and A. Chattopadhyay,“A new high throughput and area efficient SHA-3 implementation,”in Proceedings of the 2018 IEEE International Symposium on Circuits and Systems (ISCAS-2018),Florence,May2018,pp. 1–5,DOI: 10.1109/ISCAS.2018.8351649.
@inproceedings{wong2018newSMAT,
title
=
{A New High Throughput and Area Efficient {SHA-3} Implementation},
author
=
{Wong, Ming Ming and Haj-Yahya, Jawad and Suman, Sau and Chattopadhyay, Anupam},
booktitle
=
{Proceedings of the 2018 IEEE International Symposium on Circuits and Systems (ISCAS-2018)},
year
=
{2018},
month
=
may,
pages
=
{1--5},
location
=
{Florence},
doi
=
{10.1109/ISCAS.2018.8351649}
}
[32]
V. Pudi, A. Chattopadhyay, and K. Y. Lam,“Efficient and lightweight quantized compressive sensing using mu-law,”in Proceedings of the 2018 IEEE International Symposium on Circuits and Systems (ISCAS-2018),Florence,May2018,pp. 1–5,DOI: 10.1109/ISCAS.2018.8351505.
@inproceedings{pudi2018efficientSMAT,
title
=
{Efficient and Lightweight Quantized Compressive Sensing Using Mu-law},
author
=
{Pudi, Vikramkumar and Chattopadhyay, Anupam and Lam, Kwok Yan},
booktitle
=
{Proceedings of the 2018 IEEE International Symposium on Circuits and Systems (ISCAS-2018)},
year
=
{2018},
month
=
may,
pages
=
{1--5},
location
=
{Florence},
doi
=
{10.1109/ISCAS.2018.8351505},
}
[31]
S. Kumar, J. Haj-Yahya, and A. Chattopadhyay,“Efficient hardware accelerator for NORX authenticated encryption,”in Proceedings of the 2018 IEEE International Symposium on Circuits and Systems (ISCAS-2018),Florence,May2018,pp. 195–198,DOI: 10.1109/ISCAS.2018.8351145.
@inproceedings{kumar2018efficientSMAT,
title
=
{Efficient Hardware Accelerator for {NORX} Authenticated Encryption},
author
=
{Kumar, Sachin and Haj-Yahya, Jawad and Chattopadhyay, Anupam},
booktitle
=
{Proceedings of the 2018 IEEE International Symposium on Circuits and Systems (ISCAS-2018)},
year
=
{2018},
month
=
may,
pages
=
{195--198},
location
=
{Florence},
doi
=
{10.1109/ISCAS.2018.8351145},
}
[30]
T. Vatwani, A. Dutt, D. Bhattacharjee, and A. Chattopadhyay,“Floating point multiplication mapping on ReRAM based in-memory computing architecture,”in Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems (VLSID),Pune, India,Apr.2018,pp. 439–444,DOI: 10.1109/VLSID.2018.104.
@inproceedings{vatwani2018FloatingSMAT,
title
=
{Floating Point Multiplication Mapping on {ReRAM} Based in-memory Computing Architecture},
author
=
{Vatwani, Tarun and Dutt, Arko and Bhattacharjee, Debjyoti and Chattopadhyay, Anupam},
booktitle
=
{Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems (VLSID)},
year
=
{2018},
month
=
apr,
pages
=
{439--444},
location
=
{Pune, India},
doi
=
{10.1109/VLSID.2018.104},
}
[29]
D. Bhattacharjee, L. Amaru, and A. Chattopadhyay,“Technology-aware logic synthesis for ReRAM based in-memory computing,”in Proceedings of the 2018 Design, Automation Test in Europe Conference Exhibition (DATE),Dresden, Germany,Mar.2018,pp. 1435–1440,DOI: 10.23919/DATE.2018.8342237.
@inproceedings{Bhattacharjee2018TechnologySMAT,
title
=
{Technology-aware Logic Synthesis for {ReRAM} Based In-memory Computing},
author
=
{Bhattacharjee, Debjyoti and Amaru, Luca and Chattopadhyay, Anupam},
booktitle
=
{Proceedings of the 2018 Design, Automation Test in Europe Conference Exhibition (DATE)},
year
=
{2018},
month
=
mar,
pages
=
{1435--1440},
location
=
{Dresden, Germany},
doi
=
{10.23919/DATE.2018.8342237},
}
[28]
M. Khairallah, R. Sadhukhan, R. Samanta, J. Breier, S. Bhasin, R. S. Chakraborty, A. Chattopadhyay, and D. Mukhopadhyay,“DFARPA: differential fault attack resistant physical design automation,”in Proceedings of the 2018 Design, Automation Test in Europe Conference and Exhibition (DATE),Dresden, Germany,Mar.2018,pp. 1171–1174,DOI: 10.23919/DATE.2018.8342190.
{Khairallah, Mustafa and Sadhukhan, Rajat and Samanta, Radhamanjari and Breier, Jakub and Bhasin, Shivam and Chakraborty, Rajat Subhra and Chattopadhyay, Anupam and Mukhopadhyay, Debdeep},
booktitle
=
{Proceedings of the 2018 Design, Automation Test in Europe Conference and Exhibition (DATE)},
year
=
{2018},
month
=
mar,
pages
=
{1171--1174},
location
=
{Dresden, Germany},
doi
=
{10.23919/DATE.2018.8342190},
}
[27]
V. Pudi, A. Chattopadhyay, and K. Y. Lam,“Secure and lightweight compressive sensing using stream cipher,”IEEE Transactions on Circuits and Systems II: Express Briefs,vol. 65,pp. 371–375,Mar.2018,ISSN: 1549-7747,DOI: 10.1109/TCSII.2017.2715659.
@article{pudi2018secureSMAT,
title
=
{Secure and Lightweight Compressive Sensing Using Stream Cipher},
author
=
{Pudi, Vikramkumar and Chattopadhyay, Anupam and Lam, Kwok Yan},
journal
=
{IEEE Transactions on Circuits and Systems II: Express Briefs},
volume
=
{65},
year
=
{2018},
month
=
mar,
pages
=
{371--375},
issn
=
{1549-7747},
doi
=
{10.1109/TCSII.2017.2715659},
}
[26]
S. K. Lam, G. Jiang, M. Wu, and B. Cao,“Area-time efficient streaming architecture for FAST and BRIEF detector,”IEEE Transactions on Circuits and Systems II: Express Briefs,vol. 66,no. 2,IEEE,pp. 282–286,Feb.2018,DOI: 10.1109/TCSII.2018.2846683.
@article{Lam2018AreaSMAT,
title
=
{Area-time Efficient Streaming Architecture for {FAST} and {BRIEF} Detector},
author
=
{Lam, Siew Kei and Jiang, Guiyuan and Wu, Meiqing and Cao, Bin},
journal
=
{IEEE Transactions on Circuits and Systems II: Express Briefs},
volume
=
{66},
number
=
{2},
pages
=
{282--286},
year
=
{2018},
month
=
feb,
publisher
=
{IEEE},
doi
=
{10.1109/TCSII.2018.2846683},
}
[25]
A. Burg, A. Chattopadhyay, and K. Y. Lam,“Wireless communication and security issues for cyber-physical systems and the internet-of-things,”Proceedings of the IEEE,vol. 106,pp. 38–60,Jan.2018,DOI: 10.1109/JPROC.2017.2780172.
@article{Andreas2018wirelessSMAT,
title
=
{Wireless Communication and Security Issues for Cyber-physical Systems and the Internet-of-things},
author
=
{Burg, Andreas and Chattopadhyay, Anupam and Lam, Kwok Yan},
journal
=
{Proceedings of the IEEE},
year
=
{2018},
month
=
jan,
volume
=
{106},
pages
=
{38--60},
doi
=
{10.1109/JPROC.2017.2780172},
}
[24]
M. Wu, S. K. Lam, and T. Srikanthan,“A framework for fast and robust visual odometry,”IEEE Transactions on Intelligent Transportation Systems,vol. 18,no. 12,pp. 3433–3448,Dec.2017,DOI: 10.1109/TITS.2017.2685433.
@article{wu2017frameworkSMAT,
title
=
{A Framework for Fast and Robust Visual Odometry},
author
=
{Wu, Meiqing and Lam, Siew Kei and Srikanthan, Thambipillai},
journal
=
{IEEE Transactions on Intelligent Transportation Systems},
volume
=
{18},
number
=
{12},
year
=
{2017},
month
=
dec,
pages
=
{3433--3448},
doi
=
{10.1109/TITS.2017.2685433},
}
[23]
S. K. Lam, R. K. Bijarniya, and M. Wu,“Lowering dynamic power in stream-based harris corner detection architecture,”in Proceedings of the 2017 International Conference on Field Programmable Technology (ICFPT),Melbourne, VIC, Australia,Dec.2017,pp. 176–182,DOI: 10.1109/FPT.2017.8280136.
@inproceedings{lam2017loweringSMAT,
title
=
{Lowering Dynamic Power in Stream-based Harris Corner Detection Architecture},
author
=
{Lam, Siew Kei and Bijarniya, Rakesh Kumar and Wu, Meiqing},
booktitle
=
{Proceedings of the 2017 International Conference on Field Programmable Technology (ICFPT)},
year
=
{2017},
month
=
dec,
pages
=
{176--182},
location
=
{Melbourne, VIC, Australia},
doi
=
{10.1109/FPT.2017.8280136},
}
[22]
G. R. Jagadeesh and T. Srikanthan,“Online map-matching of noisy and sparse location data with hidden markov and route choice models,”IEEE Transactions on Intelligent Transportation Systems,vol. 18,no. 9,pp. 2423–2434,Dec.2017,DOI: 10.1109/TITS.2017.2647967.
@article{jagadeesh2017onlineSMAT,
title
=
{Online Map-matching of Noisy and Sparse Location Data with Hidden Markov and Route Choice Models},
author
=
{Jagadeesh, George Rosario and Srikanthan, Thambipillai},
journal
=
{IEEE Transactions on Intelligent Transportation Systems},
volume
=
{18},
number
=
{9},
year
=
{2017},
month
=
dec,
pages
=
{2423--2434},
doi
=
{10.1109/TITS.2017.2647967},
}
[21]
A. Chattopadhyay and K. Y. Lam,“Security of autonomous vehicle as a cyber-physical system,”in Proceedings of the 7th IEEE International Symposium on Embedded Computing and System Design (ISED-2017),India,Dec.2017,pp. 1–6,DOI: 10.1109/ISED.2017.8303906.
@inproceedings{chattopadhyay2017securitySMAT,
title
=
{Security of Autonomous Vehicle as a Cyber-physical System},
author
=
{Chattopadhyay, Anupam and Lam, Kwok Yan},
booktitle
=
{Proceedings of the 7th IEEE International Symposium on Embedded Computing and System Design (ISED-2017)},
year
=
{2017},
month
=
dec,
pages
=
{1--6},
location
=
{India},
doi
=
{10.1109/ISED.2017.8303906}
}
[20]
S.-K. Lam, T. C. Lim, M. Wu, B. Cao, and B. Jasani,“Data-path unrolling with logic folding for area-time-efficient FPGA-based FAST corner detector,”Journal of Real-Time Image Processing,Oct.2017,DOI: 10.1007/s11554-017-0725-0.
@article{Lam2017DataSMAT,
title
=
{Data-path Unrolling with Logic Folding for Area-time-efficient {FPGA}-based {FAST} Corner Detector},
author
=
{Lam, Siew-Kei and Lim, Teck Chuan and Wu, Meiqing and Cao, Bin and Jasani, Bhavan},
journal
=
{Journal of Real-Time Image Processing},
year
=
{2017},
month
=
oct,
doi
=
{10.1007/s11554-017-0725-0},
}
[19]
C. Zhou, M. Wu, and S. K. Lam,“Fast and accurate pedestrian detection using dual-stage group cost-sensitive realboost with vector form filters,”in Proceedings of the 25th ACM Multimedia,Mount View, USA,Oct.2017,pp. 735–743,DOI: 10.1145/3123266.3123303.
@inproceedings{zhou2017fastSMAT,
title
=
{Fast and Accurate Pedestrian Detection using Dual-stage Group Cost-sensitive RealBoost with Vector Form Filters},
author
=
{Zhou, Chengju and Wu, Meiqing and Lam, Siew Kei},
booktitle
=
{Proceedings of the 25th ACM Multimedia},
year
=
{2017},
month
=
oct,
pages
=
{735--743},
location
=
{Mount View, USA},
doi
=
{10.1145/3123266.3123303},
}
[18]
K. Garg, A. Prakash, and T. Srikanthan,“Low complexity techniques for robust real-time traffic incident detection,”in Proceedings of the 20th IEEE International Conference on Intelligent Transportation Systems (ITSC),Yokohama, Japan,Oct.2017,pp. 1–8,DOI: 10.1109/ITSC.2017.8317740.
@inproceedings{garg2017lowSMAT,
title
=
{Low Complexity Techniques for Robust Real-time Traffic Incident Detection},
author
=
{Garg, Kratika and Prakash, Alok and Srikanthan, Thambipillai},
booktitle
=
{Proceedings of the 20th IEEE International Conference on Intelligent Transportation Systems (ITSC)},
year
=
{2017},
month
=
oct,
pages
=
{1--8},
location
=
{Yokohama, Japan},
doi
=
{10.1109/ITSC.2017.8317740},
}
[17]
T. Perera, A. Prakash, and T. Srikanthan,“A scalable heuristic algorithm for demand responsive transportation for first mile transit,”in Proceedings of the 21st IEEE International Conference on Intelligent Engineering Systems,Larnaca, Cyprus,Oct.2017,pp. 157–162,DOI: 10.1109/INES.2017.8118547.
@inproceedings{perera2017scalableSMAT,
title
=
{A Scalable Heuristic Algorithm for Demand Responsive Transportation for First Mile Transit},
author
=
{Perera, Thilina and Prakash, Alok and Srikanthan, Thambipillai},
booktitle
=
{Proceedings of the 21st IEEE International Conference on Intelligent Engineering Systems},
year
=
{2017},
month
=
oct,
pages
=
{157--162},
location
=
{Larnaca, Cyprus},
doi
=
{10.1109/INES.2017.8118547},
}
[16]
S. D. Kumar, S. Patranabis, J. Breier, D. Mukhopadhyay, S. Bhasin, A. Chattopadhyay, and A. Baksi,“A practical fault attack on ARX-like ciphers with a case study on ChaCha20,”in Proceedings of the 2017 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC),Taipei, Taiwan,Sep.2017,pp. 33–40,DOI: 10.1109/FDTC.2017.14.
@inproceedings{kumar2017practicalSMAT,
title
=
{A Practical Fault Attack on {ARX}-like Ciphers with a Case Study on {ChaCha20}},
author
=
{Kumar, SV Dilip and Patranabis, Sikhar and Breier, Jakub and Mukhopadhyay, Debdeep and Bhasin, Shivam and Chattopadhyay, Anupam and Baksi, Anubhab},
booktitle
=
{Proceedings of the 2017 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC)},
year
=
{2017},
month
=
sep,
pages
=
{33--40},
location
=
{Taipei, Taiwan},
doi
=
{10.1109/FDTC.2017.14},
}
[15]
C. Zhou, M. Wu, and S. K. Lam,“Group cost-sensitive boosting with multi-scale decorrelated filters for pedestrian detection,”in Proceedings of the Twenty Eighth British Machine Vision Conference,London, UK:BMVA Press,Sep.2017,pp. 48.1–48.12,DOI: 10.5244/C.31.48.
@inproceedings{zhou2017groupSMAT,
title
=
{Group Cost-sensitive Boosting with Multi-scale Decorrelated Filters for Pedestrian Detection},
author
=
{Zhou, Chengju and Wu, Meiqing and Lam, Siew Kei},
booktitle
=
{Proceedings of the Twenty Eighth British Machine Vision Conference},
year
=
{2017},
month
=
sep,
pages
=
{48.1--48.12},
location
=
{London, UK},
doi
=
{10.5244/C.31.48},
publisher
=
{BMVA Press},
}
[14]
S. P. Kadiyala, V. K. Pudi, and S. K. Lam,“Approximate compressed sensing for hardware-efficient image compression,”in Proceedings of the 30th IEEE International System-on-Chip Conference (SOCC),Munich, Germany,Sep.2017,pp. 340–345,DOI: 10.1109/SOCC.2017.8226074.
@inproceedings{kadiyala2017approximateSMAT,
title
=
{Approximate Compressed Sensing for Hardware-efficient Image Compression},
author
=
{Kadiyala, Sai Praveen and Pudi, Vikram Kumar and Lam, Siew Kei},
booktitle
=
{Proceedings of the 30th IEEE International System-on-Chip Conference (SOCC)},
year
=
{2017},
month
=
sep,
pages
=
{340--345},
location
=
{Munich, Germany},
doi
=
{10.1109/SOCC.2017.8226074},
}
[13]
G. Jiang, S. K. Lam, S. Yidan, L. Tu, and J. Wu,“Joint charging tour planning and depot positioning for wireless sensor networks using mobile chargers,”IEEE/ACM Transactions on Networking,vol. 25,pp. 2250–2266,Aug.2017,ISSN: 1063-6692,DOI: 10.1109/TNET.2017.2684159.
@article{jiang2017jointSMAT,
title
=
{Joint Charging Tour Planning and Depot Positioning for Wireless Sensor Networks Using Mobile Chargers},
author
=
{Jiang, Guiyuan and Lam, Siew Kei and Yidan, Sun and Tu, Lijia and Wu, Jigang},
journal
=
{IEEE/ACM Transactions on Networking},
volume
=
{25},
year
=
{2017},
month
=
aug,
pages
=
{2250--2266},
issn
=
{1063-6692},
doi
=
{10.1109/TNET.2017.2684159},
}
[12]
D. Wijesundera, A. Ihalage, A. Prakash, and T. Srikanthan,“High speed performance estimation of embedded hard-core processors in FPGA-based socs,”in Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies,Bochum, Germany,Jun.2017,pp. 2:1–2:6,ISBN: 978-1-4503-5316-8,DOI: 10.1145/3120895.3120902.
@inproceedings{wijesundera2017highSMAT,
title
=
{High Speed Performance Estimation of Embedded Hard-core Processors in {FPGA}-based SoCs},
author
=
{Wijesundera, Deshya and Ihalage, Achintha and Prakash, Alok and Srikanthan, Thambipillai},
booktitle
=
{Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies},
year
=
{2017},
month
=
jun,
pages
=
{2:1--2:6},
location
=
{Bochum, Germany},
isbn
=
{978-1-4503-5316-8},
doi
=
{10.1145/3120895.3120902},
}
[11]
K. Herath, A. Prakash, J. Guiyuan, and T. Srikanthan,“Communication-aware partitioning for energy optimization of large FPGA designs,”in Proceedings of the on Great Lakes Symposium on VLSI 2017,Banff, Alberta, Canada,May2017,pp. 407–410,DOI: 10.1145/3060403.3060441.
@inproceedings{Herath2017CPECommunicationSMAT,
title
=
{Communication-aware Partitioning for Energy Optimization of Large {FPGA} Designs},
author
=
{Herath, Kalindu and Prakash, Alok and Guiyuan, Jiang and Srikanthan, Thambipillai},
booktitle
=
{Proceedings of the on Great Lakes Symposium on VLSI 2017},
year
=
{2017},
month
=
may,
pages
=
{407--410},
location
=
{Banff, Alberta, Canada},
doi
=
{10.1145/3060403.3060441},
}
[10]
A. Chattopadhyay, A. Prakash, and M. Shafique,“Secure cyber-physical systems: current trends, tools and open research problems,”in Proceedings of the 2017 Design, Automation Test in Europe Conference (DATE),Lausanne, Switzerland,Mar.2017,pp. 1104–1109,DOI: 10.23919/DATE.2017.7927154.
@inproceedings{chattopadhyay2017secureSMAT,
title
=
{Secure Cyber-physical Systems: Current Trends, Tools and Open Research Problems},
author
=
{Chattopadhyay, Anupam and Prakash, Alok and Shafique,Muhammad},
booktitle
=
{Proceedings of the 2017 Design, Automation Test in Europe Conference (DATE)},
year
=
{2017},
month
=
mar,
pages
=
{1104--1109},
location
=
{Lausanne, Switzerland},
doi
=
{10.23919/DATE.2017.7927154},
}
[9]
D. Bhattacharjee, V. Pudi, and A. Chattopadhyay,“SHA-3 implementation using reram based in-memory computing architecture,”in Proceedings of the 18th International Symposium on Quality Electronic Design (ISQED),Santa Clara, CA, USA,Mar.2017,pp. 325–330,DOI: 10.1109/ISQED.2017.7918336.
@inproceedings{bhattacharjee2017shaSMAT,
title
=
{{SHA-3} Implementation Using ReRAM based In-memory Computing Architecture},
author
=
{Bhattacharjee, Debjyoti and Pudi, Vikramkumar and Chattopadhyay, Anupam},
booktitle
=
{Proceedings of the 18th International Symposium on Quality Electronic Design (ISQED)},
year
=
{2017},
month
=
mar,
pages
=
{325--330},
location
=
{Santa Clara, CA, USA},
doi
=
{10.1109/ISQED.2017.7918336},
}
[8]
A. Easwaran, A. Chattopadhyay, and S. Bhasin,“A systematic security analysis of real-time cyber-physical systems,”in Proceedings of the 22nd Asia and South Pacific Design Automation Conference (ASP-DAC),Chiba, Japan,Jan.2017,pp. 206–213,DOI: 10.1109/ASPDAC.2017.7858321.
@inproceedings{easwaran2017systematicSMAT,
title
=
{A Systematic Security Analysis of Real-time Cyber-physical Systems},
author
=
{Easwaran, Arvind and Chattopadhyay, Anupam and Bhasin, Shivam},
booktitle
=
{Proceedings of the 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)},
year
=
{2017},
month
=
jan,
pages
=
{206--213},
location
=
{Chiba, Japan},
doi
=
{10.1109/ASPDAC.2017.7858321},
}
[7]
V. Pudi, A. Chattopadhyay, and T. Srikanthan,“Modified projected landweber method for compressive-sensing reconstruction of images with non-orthogonal matrices,”in Proceedings of the 2016 International Symposium on Integrated Circuits (ISIC),Singapore,Dec.2016,pp. 1–4,DOI: 10.1109/ISICIR.2016.7829716.
@inproceedings{pudi2016modifiedSMAT,
title
=
{Modified Projected Landweber Method for Compressive-sensing Reconstruction of Images with Non-orthogonal Matrices},
author
=
{Pudi, Vikramkumar and Chattopadhyay, Anupam and Srikanthan, Thambipillai},
booktitle
=
{Proceedings of the 2016 International Symposium on Integrated Circuits (ISIC)},
year
=
{2016},
month
=
dec,
pages
=
{1--4},
location
=
{Singapore},
doi
=
{10.1109/ISICIR.2016.7829716},
}
[6]
D. Wijesundera, A. Prakash, and T. Srikanthan,“Rapid design space exploration for soft core processor customization and selection,”in Proceedings of the 2016 International Conference on Field-Programmable Technology (FPT),Xi'an, China,Dec.2016,pp. 185–188,DOI: 10.1109/FPT.2016.7929529.
@inproceedings{wijesundera2016rapidSMAT,
title
=
{Rapid Design Space Exploration for Soft Core Processor Customization and Selection},
author
=
{Wijesundera, Deshya and Prakash, Alok and Srikanthan, Thambipillai},
booktitle
=
{Proceedings of the 2016 International Conference on Field-Programmable Technology (FPT)},
year
=
{2016},
month
=
dec,
pages
=
{185--188},
location
=
{Xi'an, China},
doi
=
{10.1109/FPT.2016.7929529},
}
[5]
G. R. Jagadeesh and T. Srikanthan,“Heuristic optimizations for high-speed low-latency online map matching with probabilistic sequence models,”in Proceedings of the 19th International Conference on Intelligent Transportation Systems (ITSC 2016),Rio de Janeiro, Brazil,Nov.2016,pp. 2565–2570,DOI: 10.1109/ITSC.2016.7795968.
@inproceedings{jagadeesh2016heuristicSMAT,
title
=
{Heuristic Optimizations for High-speed Low-latency Online Map Matching with Probabilistic Sequence Models},
author
=
{Jagadeesh, George Rosario and Srikanthan, Thambipillai},
booktitle
=
{Proceedings of the 19th International Conference on Intelligent Transportation Systems (ITSC 2016)},
year
=
{2016},
month
=
nov,
pages
=
{2565--2570},
location
=
{Rio de Janeiro, Brazil},
doi
=
{10.1109/ITSC.2016.7795968},
}
[4]
M. Wu, C. Zhou, and T. Srikanthan,“Robust and low complexity obstacle detection and tracking,”in 2016 IEEE 19th International Conference on Intelligent Transportation Systems (ITSC),Brazil,Nov.2016,pp. 1249–1254,DOI: 10.1109/ITSC.2016.7795717.
@inproceedings{Wu2016RobustSMAT,
title
=
{Robust and Low Complexity Obstacle Detection and Tracking},
author
=
{Wu, Meiqing and Zhou, Chengju and Srikanthan, Thambipillai},
booktitle
=
{2016 IEEE 19th International Conference on Intelligent Transportation Systems (ITSC)},
year
=
{2016},
month
=
nov,
pages
=
{1249--1254},
location
=
{Brazil},
doi
=
{10.1109/ITSC.2016.7795717},
}
[3]
A. Chattopadhyay, V. Pudi, A. Baksi, and T. Srikanthan,“FPGA based cyber security protocol for automated traffic monitoring systems: proposal and implementation,”in Proceedings of the 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI),Pittsburgh, PA, USA,Jul.2016,pp. 18–23,DOI: 10.1109/ISVLSI.2016.97.
@inproceedings{chattopadhyay2016fpgaSMAT,
title
=
{{FPGA} Based Cyber Security Protocol for Automated Traffic Monitoring Systems: Proposal and Implementation},
author
=
{Chattopadhyay, Anupam and Pudi, Vikramkumar and Baksi, Anubhab and Srikanthan, Thambipillai},
booktitle
=
{Proceedings of the 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)},
year
=
{2016},
month
=
jul,
pages
=
{18--23},
location
=
{Pittsburgh, PA, USA},
doi
=
{10.1109/ISVLSI.2016.97},
}
[2]
D. Wijesundera, A. Prakash, S. K. Lam, and T. Srikanthan,“Exploiting configuration dependencies for rapid area-efficient customization of soft-core processors,”in Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems,Sankt Goar, Germany,May2016,pp. 163–172,ISBN: 978-1-4503-4320-6,DOI: 10.1145/2906363.2906385.
@inproceedings{wijesundera2016exploitingSMAT,
title
=
{Exploiting Configuration Dependencies for Rapid Area-efficient Customization of Soft-core Processors},
author
=
{Wijesundera, Deshya and Prakash, Alok and Lam, Siew Kei and Srikanthan, Thambipillai},
booktitle
=
{Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems},
year
=
{2016},
month
=
may,
pages
=
{163--172},
location
=
{Sankt Goar, Germany},
isbn
=
{978-1-4503-4320-6},
doi
=
{10.1145/2906363.2906385},
}
[1]
K. Garg, S. K. Lam, T. Srikanthan, and A. Vedika,“Real-time road traffic density estimation using block variance,”in Proceedings of the 2016 IEEE Winter Conference on Applications of Computer Vision (WACV),Lake Placid, NY, USA,Mar.2016,pp. 1–9,DOI: 10.1109/WACV.2016.7477607.
@inproceedings{garg2016realSMAT,
title
=
{Real-time Road Traffic Density Estimation Using Block Variance},
author
=
{Garg, Kratika and Lam, Siew Kei and Srikanthan, Thambipillai and Vedika, Agarwal},
booktitle
=
{Proceedings of the 2016 IEEE Winter Conference on Applications of Computer Vision (WACV)},
year
=
{2016},
month
=
mar,
pages
=
{1--9},
location
=
{Lake Placid, NY, USA},
doi
=
{10.1109/WACV.2016.7477607},
}
Other Output
[2]
M. Alam, S. Bhattacharya, D. Mukhopadhyay, and A. Chattopadhyay,“RAPPER: ransomware prevention via performance counters,”Cryptography and Security,vol. 25,pp. 1–7,Feb.2018.
@article{alam2018rapperSMAT,
title
=
{{RAPPER}: Ransomware Prevention via Performance Counters},
author
=
{Alam, Manaar and Bhattacharya, Sarani and Mukhopadhyay, Debdeep and Chattopadhyay, Anupam},
journal
=
{Cryptography and Security},
volume
=
{25},
year
=
{2018},
month
=
feb,
pages
=
{1--7},
url
=
{https://arxiv.org/abs/1802.03909},
}
[1]
S. Kumar, J. Haj-Yahya, M. Khairallah, M. Elmohr, and A. Chattopadhyay,“A comprehensive performance analysis of hardware implementations of CAESAR candidates,”in Cryptology ePrint Archive, Report 2017/1261, 2017,2017,pp. 1–16.
@inproceedings{Kumar2017ASMAT,
title
=
{A Comprehensive Performance Analysis of Hardware Implementations of {CAESAR} Candidates},
author
=
{Kumar, Sachin and Haj-Yahya, Jawad and Khairallah, Mustafa and Elmohr, Mahmoud and Chattopadhyay, Anupam},